System of transferring data in a multi-cpu arrangement using address

Abstract

A system for transferring digital signals between at least two printed circuit boards (packages) provided within a digital signal processing apparatus and each mounting a plurality of electronic parts such as microprocessors between a CPU package and a peripheral control package. The CPU package has a microprocessor (CPU), a transmitting sequential address generator 1, a receiving sequential address generator circuit 1, a transmitting dual port RAM 1 and a receiving dual port RAM 1. The peripheral control package has a digital processing circuit, a transmitting sequential address generator 2, a receiving sequential address generator 2, a transmitting dual port RAM 2 and a receiving dual port RAM. When a control information is to be sent from the CPU to the digital processing circuit, the CPU is required to only write the control information in the transmitting dual port RAM. The control information is read out from the transmitting dual port RAM according to sequential addresses produced by the transmitting sequential address generator independently from the CPU and outputted to the receiving dual port RAM of the peripheral control package. The control information thus outputted is written in the receiving dual port RAM 2 according to addresses produced by the receiving sequential address generator 2. The digital processing circuit reads the control information from the receiving dual port RAM 2 and processes it in a manner predetermined. This is the same for a case where information is transferred from the digital processing circuit to the CPU.