Synchronizing circuit and method

Abstract

Synchronization with an incoming digital signal is timed at a midpoint of the incoming bits by selecting a fine sampling interval that is smaller than the transition period between bits and taking plural adjacent samples, e.g., three samples at the fine sampling interval in a sampling period greater than two bit periods and determining if all the samples were taken from the same bit. If not, either a leftmost or rightmost sample must be unequal to the other samples and the relative timing or phase of the plural samples are shifted right or left in the next sampling period, in a direction opposite from the detected unequal sample, and plural fine samples are again taken, beginning at the newly shifted point. Once all the samples are equal, the spacing of the plural samples is increased gradually until an inequality is again encountered, at which point another shift of the middle sample in the same direction occurs, by an amount equal to the fine interval, and the process is repeated with ever increasing spacing between the plural samples until the samples span an entire bit period and a middle sample is centered thereon. The relative timing or phase of this middle sample can be used to synchronize on the incoming digital signal so that the synchronization is made at the midpoint of the incoming bits.