The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
Jun. 19, 1991
Applicant:
Inventor:
Marc E Levitt, Sunnyvale, CA (US);
Assignee:
Sun Microsystems, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
371 221 ; 364488 ; 364579 ; 364580 ; 371 226 ;
Abstract
A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.
Levitt, Marc. (1994). Method and apparatus for improving fault coverage of system logic of an (U.S. Patent No. 5341382). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5341382
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