Flash memory cell structure

Abstract

A semiconductor flash memory cell which includes a P type substrate with an N type well formed therein followed by a P type well formed within the N well. An N type drain is formed in the P well as is an N type source, with the drain and source being spaced apart so as to create a channel region therebetween. A floating gate is disposed over only a part of the channel and a first segment of a control gate is disposed over the remainder of the channel. A second segment of the control gate is disposed over the floating gate. The arrangement of the floating and control gate functions to eliminate adverse effects of over erase. In addition, the well-within-a-well structure enables biasing voltages to be applied during erase which forces electrons removed from the floating gate to enter the channel region, rather than the drain region thereby increasing the program/erase cycle endurance of the cell.