The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
Sep. 01, 1993
Tadashi Maruyama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
An input terminal inputs an input signal oscillating between a first power source voltage and second power source voltage according to a selected mode and a non-selected mode. An output terminal delivers a signal oscillating between the first and second power source voltages and a third power source voltage according to voltage conversion and non-voltage conversion. An N-channel E type transistor of a positive threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with the second power source voltage. An N-channel I type transistor of a neutral threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with a control signal oscillating between the first power source voltage and the second power source voltage, the control signal determining whether or not a voltage conversion is made. A charge pump circuit is connected to the output terminal and operative with the first, second and third power source voltages such that the charge pump circuit is rendered an active state only when the voltage conversion is mode. A predetermined number of level shifter circuits having an arrangement as set out above are connected between row and column decoders of an EEPROM on one hand and a cell matrix array on the other hand.