The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
May. 11, 1992
Gerhard P Fettweis, Berkeley, CA (US);
Herbert R Dawid, Aachen, DE;
Teknekron Communications Systems, Inc., Berkeley, CA (US);
Abstract
A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm: Q.sub.w 1 I=W-1 to 0 N=N-D S=Signbit (N) Q.sub.I =S (EXOR) Q.sub.I+1 N=.vertline.N.vertline. D=D/2 END A recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.