The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
Mar. 13, 1992
Hisao Niwa, Osaka, JP;
Kazuhiro Kayashima, Hirakata, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCO.sub.f and a continuous cyclic logic value CV.sub.f at a preselected line G.sub.f in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CT.sub.f by the use of the controllability cost CCO.sub.f and the continuous cyclic logic value CV.sub.f for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CT.sub.f, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.