The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 1994

Filed:

Jul. 12, 1993
Applicant:
Inventor:

Takeshi Yamamura, Zama, JP;

Assignee:

Fujitsu Limited, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G06F / ;
U.S. Cl.
CPC ...
324765 ; 324 731 ; 371 223 ;
Abstract

A semiconductor integrated circuit device in which a scan circuit is self-contained, is adapted to implement a dynamic burn-in test within an LSI device. The device includes an internal circuit provided in an LSI chip; a scan circuit for delivering scan data into the internal circuit; scan data generation circuit for generating scan data corresponding to a test mode signal; and a clock generation circuit for generating scan clocks corresponding to the test mode signal. In the internal circuit, the scan circuit, the scan data generation circuit and the clock generation circuit are arranged in the LSI chip. Corresponding to the test mode signal, data produced by the scan data generation circuit is delivered to the scan circuit.


Find Patent Forward Citations

Yamamura, Takeshi. (1994). Semiconductor integrated circuit having a scan circuit provided with a (U.S. Patent No. 5341096). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5341096

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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