The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
Aug. 10, 1992
Chih-Liang Chen, Briarcliff Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A BiCMOS circuit including an NFET transistor connected as a diode is disclosed. The NFET transistor provides a threshold level for sourcing current. A PFET transistor and a clamping diode are connected in parallel to serve as a current path to the base of a bipolar emitter follower transistor. The emitter follower transistor and an NFET transistor act as pull-up and pull-down devices at the output stage. The NFET-diode turns off the current in the logic network as well as in the output buffer when the inputs are at a low logic level. As a result, the power consumed by this NTL based BiCMOS circuit is lower compared to that of an ECL based BiCMOS circuit. Also the drawbacks of a conventional NTL circuit, low noise immunity and signal degradation, are eliminated because the NFET-diode serves as a reference level for input signals. An additional embodiment wherein CMOS logic is cascoded with the existing bipolar logic to allow a higher logic function is also disclosed. The circuit of this invention can provide a single-phase output which is compatible with a low-voltage ECL/BiCMOS signal.