The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 1994
Filed:
Dec. 03, 1992
Thomas E Schiltz, Chandler, AZ (US);
Carl R Nuckolls, Fountain Hills, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A sample and hold circuit is formed within an integrated circuit and has a small, substantially linear hold capacitance. The circuit includes a sampling switch, a hold capacitor, and a buffer amplifier. The buffer amplifier includes a common drain FET and a constant current source FET. The common drain FET provides an input which couples to the hold capacitor. The constant current FET isolates the source of the common drain FET from ground. The sample and hold circuit may be used as a wide bandwidth mixer. In a radio application, a pulse generator provides a stream of pulses in which the sampling rate times an integer number equals the RF frequency minus the IF frequency. The width of the sampling pulse is less than the period of an RF signal. In an oscillator application, the sample and hold circuit operates as a mixer in a frequency multiplying phase locked loop.