Phase locked loop with frequency deviation detector and decoder circuit

Abstract

A phase locked loop includes a capture aid circuit to pull the frequency of the oscillator towards the bit frequency of a data signal HF.sub.in consisting of pulses of variable lengths, each length being an integral multiple of a single bit basic length unit. The capture aid circuit includes a pulse length detector for measuring and rounding pulse length to the nearest integral number of basic length units, and determining the difference (.DELTA.RL) between the measured and rounded length value (RL). For small frequency deviations the rounding error (.DELTA.RL) signal is used as a frequency deviation control signal for increasing or decreasing the oscillator frequency. For larger frequency deviations the minimum pulse length will be either more or less than a predetermined number of length units. That is detected by supplying the rounded pulse length signal (RL) signal to a pulse length decoder which determines the presence of pulses having a minimum length below the predetermined number of units or the absence of pulses having such minimum length. From signals indicative of those conditions further control signals are derived in a frequency deviation detector, which further control signals adjust the oscillator frequency so as to bring the frequency deviation within the range in which the rounding error (.DELTA.RL) signal can be used to precisely adjust the oscillator frequency to the bit frequency of the data signal.