Semiconductor memory device

Abstract

A semiconductor memory device is adapted for storing, as a unit of memory information, multiple-bit data constituted by signal data comprised of bit data of 2.sup.n bits (n is a natural number) and remainder data comprised of bit data of C bits (C is a natural number, C<2.sup.n). This semiconductor memory device includes a plurality of circuit blocks comprising, e.g., two memory cell groups each comprised of a plurality of memory cells, and a row decoder and a column decoder adapted for allowing respective desired ones of the memory cells within the memory cell groups to be selectively active. Thus, the row decoder and the column decoder become operative so that the bit data serving as the signal data is assigned to one or plural circuit blocks by one bit or plural bits, and the bit data serving as the remainder data is assigned to any circuit block in which bit assignment has been made.