The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 1994
Filed:
Aug. 28, 1992
Ramalingam Sridhar, East Amherst, NY (US);
Seokjin Kim, Amherst, NY (US);
Yong-Chul Shin, Amherst, NY (US);
Naidu C Bogineni, Amherst, NY (US);
State University of New York, Buffalo, NY (US);
Abstract
An analog synapse circuit for an artificial neural network requiring less circuitry and interconnections than prior synapses, while affording better weight programming means uses two complementary floating-gate MOSFETs with tunneling injection in an inverter configuration, with each MOSFET storing a weight value. This weight value is set by storing a charge injected by Fowler-Nordheim tunneling, or other tunneling means, into the floating-gate, which shifts the threshold voltage of the device. A programming line applies a current pulse to the MOSFET floating gate to write or erase this stored charge, thereby adjusting the weight of the MOSFET. The two MOSFETs are connected with the gate electrodes connected together and the drain electrodes connected together to provide a common gate and common drain between the two MOSFETs. An input line is connected to the common gate, and an output line is connected to the common drain. The source electrodes of each MOSFET are connected to reference voltages. The synapse circuit may be used in either a feedforword or feedback network, and may be expanded from two to four quadrant operation. The synapse provides a single output current line which represents a function of the input voltage and the stored weights. A plurality of such synapses may be configured in a network, wherein the output lines of each synapse are connected at a current summing node at the input of a neuron. An active load in the input of the neuron allows for both excitatory and inhibitory output current from the synapse circuit.