The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 1994

Filed:

Jul. 17, 1992
Applicant:
Inventors:

Takao Kakiuchi, Takatsuki, JP;

Kazuo Sato, Takatsuki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; G11C / ;
U.S. Cl.
CPC ...
257321 ; 257622 ; 257627 ; 365185 ;
Abstract

A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film. The stress caused to the tunnel insulating film as a result of the oxidation process for forming the third gate insulating film is relieved, providing the tunnel insulating film with resistance to dielectric strength.


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