Method of manufacturing a semiconductor memory having an increased cell

Abstract

A semiconductor memory includes at least one memory cell composed of an insulated gate field effect transistor and an associated stacked capacitor which are formed close to each other on a single substrate of a first conduction type. The insulated gate field effect transistor has a source and a drain which are located separately from each other in the single substrate and formed of impurity regions of a second conduction type opposite to the first conduction type. The insulated gate field effect transistor also has a gate formed through a gate insulator on a region between the source and the drain. The gate and the source of the insulated gate field effect transistor are connected to a word line and a bit line, respectively, and the drain of the insulated gate field effect transistor is connected to a first electrode of the stacked capacitor. The memory cell also comprises a first impurity region of the first conduction type formed in the substrate below the stacked capacitor, and a second impurity region of the second conduction type which is formed above the first impurity region in the substrate below the stacked capacitor and which has a junction depth shallower than the depth of the first impurity region, so that a pn junction is formed between the first impurity region and the second impurity region. The second impurity region is connected to the first electrode of the stacked capacitor. With this arrangement, the memory cell has a cell capacitance of based on a sum of a capacitance of the stacked capacitor and a junction capacitance of the pn junction.