The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 1994

Filed:

Jun. 14, 1991
Applicant:
Inventors:

Warren W Grunbok, Poughkeepsie, NY (US);

Donald W Price, Lake Katrine, NY (US);

De Tran, Woodstock, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395425 ; 364D / ; 3642434 ; 3642443 ; 3642624 ; 395400 ;
Abstract

A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.


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