Digital interface circuit

Abstract

A digital interface for allowing a first device which receives and sends information serially to communicate with a second device which receives and sends information in parallel. The first device may be an encryption unit while the second device may be a relay/responder/reporter connected to a transmitter or a digital signal processing unit. The digital interface comprises an erasable programmable logic device which during an uplink data transfer performs the function of converting parallel logic signals, that is control signals and data words provided by the relay/responder/reporter, for example, to commands and data to be transmitted by a transmitter serially to the encryption unit. In a like manner, the erasable programmable memory device during a downlink data transfer converts serial commands and data received from the encryption unit by a receiver to a parallel format for transmission to the relay/responder/reporter. The protocol converter includes a dual port memory which is used for temporary storage of data during an information transfer from the encryption unit to the relay/responder/reporter. The protocol converter also includes a programmable array logic device for latching therein commands which are sent to the encryption unit and commands received from the encryption unit during a data transfer and a microcontroller which monitors the commands latched in the programmable array logic device. When the microcontroller fails to detect a send or receive command during an uplink or down link data transfer, the microcontroller will reset the protocol converter allowing for a restart of the data transfer.