The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 1994

Filed:

May. 19, 1993
Applicant:
Inventors:

Hideki Tamura, Moriyama, JP;

Kaoru Furukawa, Hikone, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 19 ; 363 18 ;
Abstract

An inverter power supply includes a DC supply providing a DC voltage from an AC mains, a transformer having primary, secondary, and feedback windings, and a self-excited oscillator energized by the DC supply to generate a high frequency voltage across the primary winding and induces across the secondary winding an output AC voltage for driving a load. The oscillator comprises an FET connected in series with the primary winding. A biasing capacitor is connected in series with the feedback winding across a source-gate path of FET for providing an offset voltage which is additive to a feedback voltage at the feedback winding to give a bias applied to a gate of FET so as to alternately turn on and off FET for self-excited oscillation. Also included is a bias stabilizing circuit which lowers the offset voltage by discharging the biasing capacitor through FET being turned on, thereby driving FET turned on only for substantially a constant ON-time period irrespective of an increase in the DC voltage within a limited range. The power supply is characterized to include a compensation circuit which produces a negative voltage to be superimposed to the offset voltage of the biasing capacitor, thereby enabling to lower the offset voltage negative even when the DC voltage increases over the limited range, thereby keeping the ON-time period of FET substantially constant over a wide range of variations in the DC voltage.


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