The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 1994
Filed:
Feb. 23, 1993
Mieko Suzuki, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A process for manufactoring a semiconductor device having a double- or multi-level interconnection structure is disclosed. The process includes steps of: forming a first level metal interconnect; then forming a first silicon oxide layer by PECVD, and forming a second silicon oxide layer by atmospheric CVD using tetraethoxysilane and oxygen containing ozone under a condition of excess ozone in which the ratio of flow-rate of ozone to flow-rate of tetraethoxysilane is about 20:1. An organic compound coating layer is formed by spin-coating accompanied by a thermal treatment. The organic compound coating layer and the second silicon oxide layer are etched-back to remove the compound oxide layer completely. A third silicon oxide layer is formed by PECVD; and forming a second level metal interconnect. A good planarization can be obtained and a failure, such as delamination or blister due to bumping, of the third silicon oxide layer can be avoided. Hence, a high yield and a high reliability of the semiconductor device having a double- or multi-level interconnection structure can be achieved.