Non-volatile semiconductor memory device with erasure control circuit

Abstract

A non-volatile semiconductor memory device has an erasure control circuit which, during erasure operation, is switched to a source of a memory cell having a floating gate. The erasure control circuit is constituted by a resistor element and a reference transistor having the same structure as that of the memory cell. One end of the resistor element is connected to a node which, during erasure operation, is electrically connected to the source of the memory cell. The reference transistor has a drain connected to the node, a gate connected to a constant-voltage source, and a source grounded. A floating gate/substrate insulating film of the memory cell and a floating gate/substrate insulating film of the reference transistor are formed simultaneously in the same fabrication step so that the thickness of these insulating films are substantially the same. Even when the thickness of the floating gate/substrate insulating film of the memory cell varies due to production variations, it is possible to prevent the occurrence of an over-erase or a deficient erase by making changes accordingly in the erasure voltage, that is, the voltage at the node.