The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 1994
Filed:
Apr. 20, 1992
Applicant:
Inventor:
Naoya Takahashi, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 364488 ;
Abstract
In the chip layout of an LSI, a layout near bonding pads is efficiently optimized. Especially in a chip having a large number of pins, an increase in chip size caused by pad necks can be prevented. Normal functional macro-blocks are arranged in an inner region of the LSI. On the other hand, input/output blocks including corner blocks are arranged at the peripheral portion of the LSI. In addition, pads separated from the input/output blocks are arranged on the LSI including portions near the corner blocks, and the input/output blocks and the pads are connected to each other through wiring lines.