The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 1994

Filed:

Dec. 11, 1992
Applicant:
Inventors:

David Fishbaine, Minneapolis, MN (US);

John P Konicek, Minneapolis, MN (US);

Steven K Case, St. Louis Park, MN (US);

Timothy A Skunes, Columbia Heights, MN (US);

Jeffrey A Jalkio, St. Paul, MN (US);

Assignee:

CyberOptics Corporation, Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N / ;
U.S. Cl.
CPC ...
356375 ; 356237 ;
Abstract

A high speed, high precision laser-based semiconductor lead measurement system for use on surface mount component placement machines. A multi-beam laser system is used to accurately sense the position and condition of each of the many leads used on integrated circuits prior to their placement on a surface mount circuit board by a pick and place machine. Using two, three or four laser beams, the non-contact sensor system can, with the highest degree of resolution, determine lateral orientation, height, colinearity, and coplanarity of leads for integrated circuit components, even those having an ultra-fine pitch. Determination of the lead position by the invention is based on the integrated circuit leads occluding the light of one or more precisely directed and focused laser light sources. Each integrated circuit lead is passed nominally through the focal point of a laser beam. The position of each lead is determined when it blocks all or a portion of the light of the laser beam. A processor means is used to calculate the actual position of each lead. The difference between the actual position of the lead and the nominal position of the lead can then be computed. The position of each lead is then sorted to determine the greatest deviation of any lead from a best fit line or from the Seating Plane. The processor may then either generate a reject or a repositioning signal to the component placement machine for proper placement of the integrated circuit upon the surface mount circuit board.


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