The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 1994

Filed:

Jun. 15, 1992
Applicant:
Inventor:

Chun H Wu, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ; H04N / ;
U.S. Cl.
CPC ...
348536 ; 348540 ; 348541 ; 348547 ; 331 / ; 331 17 ; 331 20 ;
Abstract

A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync. During conditions of unusable separated sync pulse signals, the microprocessor output causes the integrating capacitor or LPF to be coupled to a voltage source for forcing the VCO to a maximum frequency. Also, during periods of unusable sync the microprocessor decouples the separated sync signal from the vertical deflection generating circuit, allowing the vertical deflection generating circuits to free run. Setting the horizontal frequency to a maximum value and inhibiting vertical deflection synchronization eliminates instability of on-screen displays during periods of unusable sync.


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