The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 1994
Filed:
Mar. 08, 1993
Applicant:
Inventors:
Anil Gupta, San Jose, CA (US);
Kuo-Lung Chen, Saratoga, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365185 ; 365174 ; 365218 ;
Abstract
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.