Semiconductor memory circuit, semiconductor memory module using the

Abstract

A sequential access type memory medium of a large memory capacity is composed of a number of semiconductor memory modules, each including a semiconductor memory device and necessary peripheral circuits accommodated in a square package. The same number of terminals are provided on each of four sides of the square package. The terminals on the four sides are so wired that the same kind of signal is transferred through positionally corresponding terminals of four sides of the square package, and the terminals on one side are of a plug type and the terminals on the remaining three sides are of a socket type which can be fitted and connected with the plug type terminal so as to interconnect corresponding signal lines. In addition, positionally corresponding socket type terminals of three sides of each memory module are interconnected so as to interconnect the terminals for the same signal. Thus, a plurality of memory modules are interconnected in an arbitrary order and in arbitrary location with using no printed circuit board and with a high expandability, so that in each semiconductor memory module, an address signal is generated on the basis of the synchronous signal supplied from an external, and the synchronous signal is supplied to the just succeeding semiconductor memory circuit after the data reading of the first mentioned semiconductor memory circuit has been completed.