The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 1994
Filed:
Aug. 12, 1992
Ruey J Yu, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
An ATD pulse generator circuit (20) provides an ATD pulse at CMOS logic levels in response to a single-ended ECL level input signal transition. An emitter-follower input portion (21), a differential amplifier (23), and emitter-follower portion (25) converts the single-ended input signal to intermediate level differential signals. P-channel transistors (51 and 52) receive the intermediate level differential signals and provide complementary CMOS level outputs signals. Cross-coupled delay portion (29) prevents the N-channel transistors (55 and 56) from switching on until after a delay, causing both of the CMOS level output signals to remain at logic high levels for a predetermined time. Cross-coupling the N-channel transistors (55 and 56) also results in reduced power consumption. A NAND gate (31) receives the logic high levels and provides a CMOS level ATD pulse, the duration of which is adjustable.