Apparatus for controlling instruction execution in a pipelined processor

Abstract

A processor which is specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by way of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction. The microprocessor also has an Intel/Motorola pin whose input specifies the type of host processor the coprocessor is working with and further executes I/O instructions which permit the same code to be used with either host processor.