The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 1994

Filed:

Jul. 29, 1993
Applicant:
Inventors:

Johnnie F Molina, Tucson, AZ (US);

R Mark Stitt, II, Tucson, AZ (US);

Rodney T Burt, Tucson, AZ (US);

Assignee:

Burr-Brown Corporation, Tucson, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03G / ; H03F / ;
U.S. Cl.
CPC ...
330254 ; 330282 ; 330296 ;
Abstract

A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.


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