The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 1994
Filed:
Dec. 29, 1992
Ichiro Ishida, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A superconducting device including first and second trenches formed on a principal surface of a semiconductor substrate, separated from each other, and first and second superconductor electrodes filled in the first and second trenches and planarized to have a surface coplanar with the principal surface of the semiconductor substrate. The first and second superconductor electrodes form a separation zone which is defined by opposing sides of the first and second superconductor electrodes. An insulating layer is formed to cover a portion of the first superconductor electrode, the separation zone and a portion of the second superconductor electrode, and a gate electrode is formed on the insulating layer so as to be positioned above at least the separation zone. The above mentioned superconducting device can be formed by forming first and second trenches on a principal surface of a semiconductor substrate separate from each other, and depositing a superconductor layer so as to cover a whole of the principal surface of the semiconductor substrate. A resin layer is deposited on the whole of the principal surface of the semiconductor substrate, and etch-back is performed to completely remove the deposited resin layer and also to remove the deposited superconductor layer from a surface excluding the first and second trenches, so that the superconductor layer remaining in the first and second trenches respectively form first and second superconductor electrodes planarized to have a surface coplanar with the principal surface of the semiconductor substrate. An insulating layer and a gate electrode are formed to cover at least a separation zone between the first and second trenches.