Process for fabricating lateral pnp transistor structure and bicmos ic

Abstract

A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL. A field oxide spacer FOX is grown during the CMOS active area definition mask, etch and grow sequence for separating the PNP BC/N+SINK from the PNP collector region P+C. A uniform layer of polysilicon POLY is masked and etched during the POLY definition mask and etch sequence to form a self aligned transistor SAT POLY mask for critically defining the PNP base width and base active region. The PNP collector region P+C and emitter region P+E are introduced through the SAT POLY mask using at least one of the NPN base definition mask, etch and P type introduction sequence and PMOS P+S/D mask definition, etch and P type introduction sequence. The PNP base contact region can be formed using the NPN emitter definition mask sequence. The PNP transistor contact surfaces and metal contacts are thereafter prepared according to conventional procedures.