System for asynchronously delivering self-describing control elements

Abstract

A microprocessor system includes a processor unit, one or more subsystem adapter units, optional I/O devices which may attach to the adapters, and a bus interface. Memory in the processor and memory in the adapters are used by the system as a shared memory which is configured as a distributed First In First Out (FIFO) circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing self-describing control elements on the pipe which represent requests, replies, and status information. The units send and receive self-describing control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The distributed, shares memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements. The control elements have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.