The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 1994
Filed:
Mar. 22, 1991
Daisuke Azuma, Kyoto, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
An SRAM is provided wherein each memory cell has first and second storage nodes to be maintained at complementary potentials corresponding to storage data and first and second inverters provided in anti-parallel between the first storage node and the second storage node. Also, a DRAM is provided wherein each memory cell has a single storage node to be maintained at a potential corresponding to storage data and a capacitor provided between the storage node and a low potential source. In each of predetermined memory cells in which storage data is to be initialized, an MOS transistor, which is controlled to turn on for a fixed time period at the time of power supply, is connected between a potential source capable of supplying a potential corresponding to the initialization data and at least one of the first and the second storage nodes (in the case of the SRAM) or between the potential source and the single storage nodes (in the case of the DRAM). In the case of the SRAM, the first or the second inverter in each of the predetermined memory cells is replaced by a two-input NAND gate or a two-input NOR gate for which the output potential at the time of the power supply is controlled to correspond to the initialization data irrespective of the potential at the first (or the second) storage node.