Sample and hold voltage receiver having reduced harmonic distortion

Abstract

A high frequency sampling receiver circuit receives an analog input signal that is to be compared with a multiplicity of reference voltages. The receiver circuit includes a multiplicity of parallel sample and hold circuits, each having a respective sampling transistor connected between a respective sample holding node and a common input terminal. The receiver circuit is coupled to an array of comparator circuits, where each comparator has one input connected to one of the sample holding nodes and a second input connected to one of a sequence of reference voltages. A bias voltage circuit applies respective bias voltages to each of the sampling transistors such that the difference between the bias voltage of each sampling transistor and the reference voltage used by the corresponding comparator is approximately the same for all the sample and hold circuits. As a result, the resistance of the sampling transistors are all approximately equal for the input signal voltage range in which each sampling transistor is near its comparison point. The bias voltage circuit includes a resistive ladder circuit for generating the respective bias voltages such that the voltage difference between neighboring pairs of the bias voltages is equivalent to the voltage difference between corresponding pairs of the reference voltages.