The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 1994

Filed:

Feb. 14, 1991
Applicant:
Inventors:

John J Vaccaro, Westford, MA (US);

Willard L Eastman, Lexington, MA (US);

Thomas M Hopkinson, Woburn, MA (US);

Assignee:

The Mitre Corporation, Bedford, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 371 ; 371 35 ; 371 378 ; 364D / ; 3642599 ; 3642622 ;
Abstract

A programmable decoder that provides both error and erasure decoding for all Reed-Solomon, primitive BCH, non-primitive BCH, and binary BCH codes of any rate over any field is disclosed. The user can specify decoding parameters including the code block-length, the code-generator polynomial, and the field-generator polynomial. The basic architecture, less the small overhead for programmability, is also recommended for fixed-code applications. The decoding processor of the decoder includes systolic arrays implementing a syndrome calculator, a key equation solver, a Chien search, a recursive extender, and an inverse transform. The number of cells required for each of the five functions is on order of the error correction capability t. The systolic arrays can be fabricated on a single VLSI microchip that is itself systolic. Each of the individual systolic arrays can extended by arraying microchips together, so that any desired error correction capability can be attained by using multiple systolic microchips with a single controller.


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