Mos memory device

Abstract

A semiconductor memory device to be used as a mask ROM having: a MOS transistor array having MOS transistors disposed in a matrix of rows and columns, the drain-source circuits of the MOS transistors in each row being serially connected; a row selecting decoder for selecting one of the rows; first and second column lines alternately disposed in the row direction, each first column line being connected to one end of the drain-source circuit of each of the MOS transistors disposed in one column, and each second column line being connected to the other end of the drain-source circuit of each of the MOS transistors disposed in the one column; a data reading circuit for reading data stored in the MOS transistor array; a first switching circuit for selectively connecting one of the first column lines to the data reading circuit; a second switching circuit for selectively connecting one of the second column lines to a ground potential; and a column selecting circuit for selecting one of the columns of the MOS transistors, the column selecting circuit including a plurality of column select lines provided to the MOS transistor columns, respectively, wherein when one of the column select lines is activated, the first and second switching circuits connected to the first and second column lines connected to the MOS transistors in the corresponding column are made conductive at the same time.