Dual-port memory having a serial register accessing arrangement with

Abstract

A data processing system includes a video random access memory with a serial register having a serial register tap addressing arrangement wherein tap addresses are decoded from column address factors and are applied to data gates associated stages of the serial register accessing data from the serial register stages. A decoder responds to a code word and generates a stages select signal that controls the data gates between the serial register stages and data lines. A plurality of code word gates, interposed in the decoder inputs and responsive to a control pulse, enable the stages select signal only while the control pulse is active. By thus limiting the decoder input to pulsed code words, sequential bit interference and inadvertent bit overwriting are avoided. An equalizer circuit, connected with each data line, equalizes the potential on the data lines before the accessed data bit is applied to the selected data line.