The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 1994

Filed:

Nov. 27, 1992
Applicant:
Inventors:

Donald C Anderson, Austin, TX (US);

Keith D Dang, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
3647151 ;
Abstract

A priority encoder (12) has a most significant bit circuitry (18), a first less significant bit circuitry (20) and a second less significant bit circuitry (22). The priority encoder detects a leading one within a plurality of data bits. Each data bit is associated with a different one of a plurality of input signals. The most significant bit circuitry is coupled to a first one of the input signals and generates a first output signal and a parallel blocking signal. Both of the first output signal and the parallel blocking signal are representative in a first logic state of a leading one associated with the first signal. The first less significant bit cell is coupled to a second one of the input signals and to the parallel blocking signal. The first less significant bit cell generates a second output signal and a less significant carry signal. Both the second output signal and the less significant carry signal are representative in a first logic state of a leading one associated with the second input signal. The second less significant bit cell is coupled to a third one of the input signals, to the parallel blocking signal and to the less significant carry signal. The second less significant bit cell generates a third output signal representative in a first logic state of a leading one associated with the third input signal.


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