The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 1994
Filed:
Sep. 02, 1992
Jerome Sears, Wyckoff, NJ (US);
Walter Parfomak, Wallington, NJ (US);
Arieh J Neuwirth, Fair Lawn, NJ (US);
Walter Kluss, Kearny, NJ (US);
AlliedSignal Inc., Morris Township, Morris County, NJ (US);
Abstract
A system (10) for controlling stabilization of a synchro (26), which is driven from a digital to synchro converter (12), which utilizes a current sensor (14) to detect the magnitude of the synchro current drive signal and through a compare and hold circuit (20) compares the magnitude of the current with a predetermined maximum current and if exceeded provides a signal to a logic control (22) which controls a current limiter (16), disposed in series with the conductors providing load current to synchro (26). Current limiter (16) operates in a non-current limiting mode, wherein load current is passed unhindered to synchro (26), and a current limiting mode wherein current limiting resistors are inserted in series with the conductors carrying drive current to synchro (26). When the commanded drive current exceeds the reference current, compare and hold circuit (20) initiates a signal to cause current limiter (16) to operate in the current limiting mode. Compare and hold circuit (20) also includes a delay circuit which keeps current limiter (16) in the current limiting mode for a short period of time after the commanded drive current falls below the reference current level. A pulse width oscillator (24) provides an input to logic control (22) which causes logic control (22) to periodically switch current limiter (16) to the unlimited current condition for short periods of time even when the compare and hold circuit (20) is providing a signal requesting the current limiting mode.