The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 1994
Filed:
Jul. 30, 1991
Adrian I Cogan, San Jose, CA (US);
Neill R Thornton, Fremont, CA (US);
MicroWave Technology, Inc., Fremont, CA (US);
Abstract
The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The charge of the implanted ions is the same as the charge polarity of the gate regions. To improve the overdrive capability of a JFET a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region i.e., the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region. The second junction in the gate region of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to prior art JFETs. A new method is used to form a guard ring surrounding the active area of a JFET. The JFET formed using this method has a guard ring of a second conductivity type extending a first distance D1 into a layer having a first conductivity type and a gate region of the second conductivity type extending a second distance D2 into the layer. The method of this invention allows selection of the first and second distances D1, D2 to optimize the breakdown voltage and performance of the JFET of this invention.