Method of forming thin film pseudo-planar fet devices and structures

Abstract

A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.