Phase locked loop synchronization system for use in data communications

Abstract

A clock generator uses coarse and fine phase locking to lock an internal clock signal to an intermittently received data signal. The clock generator uses separate coarse and fine phase locked loops (PLL's). The respective voltage controlled oscillators (VCO's) of the PLL's are made from matched components and the coarse control signal is applied to both VCO's. The fine PLL locks the output signal provided by the second PLL in phase to the received data signal. The oscillatory signal provided by the second PLL is the output clock signal of the system. The fine phase control signal is combined with the coarse frequency control signal to generate the control signal for the second VCO. The fine phase control signal is generated by comparing transitions in a non-return to zero (NRZ) encoded data signal to corresponding transitions in the output clock signal. Phase correction errors made due to missing transitions in the encoded data signal are compensated by one type of phase detector which retains the previous levels of the received data signals. Another type of phase detector gates the clock signal into the loop filter only when it is coincident with detected transitions in the received data signal.