The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 1994
Filed:
Apr. 28, 1993
Steven P Larky, Austin, TX (US);
Alan W Peevers, Peekskill, NY (US);
Joe C St Clair, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A pixel-depth converter for source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth. A packed-pixel-data depacker circuit receives source-pixel data words having a packed-pixel data format from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with a user selected pixel-depth-conversion scale factor. A pixel-data-conversion-table storage circuit stores selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values corresponding to the selected pixel-depth-conversion scale factor. The storage circuit includes independently-operable converted-data-read parallel output ports and associated conversion-table read-address input ports. Conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table storage circuit. Stored conversion data can be read in parallel from the associated converted-data-read output ports. Input ports of multiplexers are connected to corresponding terminal subsets of the depacker circuit which are associated with different pixel-depth-conversion scale factor. A conversion-lookup address output port of each multiplexer is connected to an associated read-address input port of the storage circuit. The multiplexer control-signal input ports are connectable to a bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-source-pixel-data portions.