Analog to digital converter that decodes msbs from internal voltages of

Abstract

An N-bit analog to digital converter (ADC) generates an output code having J most significant bits (MSBs) and K least significant bits (LSBs). First and second folder circuits map an analog input voltage into first and second folder output voltages, each folder circuit having at least 2.sup.k +1 folding points. The folding points of the first folder circuit are located at 2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k, while the folding points of the second folder circuit are located at 3.times.2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k. Each folder circuit produces a folder output voltage as well as 2.sup.k +1 differential output voltages. An MSB decoder includes a comparator that compares the first and second folder output voltages to generate a second lowest MSB. The MSB decoder also includes a multiplexer that selects, based on the second lowest MSB, the differential output voltages from one of the two folders, and a J-2 bit decoder for decoding the selected set of differential output voltages to generate the J-2 highest MSBs. The MSB decoder also generates the lowest MSB by comparing neighboring ones of the differential output voltages from a first one of the two folder circuits using K comparator circuits. Each of the K comparator circuits is enabled by a corresponding one of the differential output voltages from the other folder circuit, and thus only one of the K comparator circuits is enabled during the conversion of each input signal. The enabled comparator's output determines the value of the lowest MSB.