The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 1994

Filed:

Nov. 18, 1992
Applicant:
Inventors:

Richard F Lyon, Los Altos, CA (US);

Tobias Delbruck, Pasadena, CA (US);

Carver A Mead, Pasadena, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
307529 ; 307355 ; 307490 ; 307498 ; 364819 ;
Abstract

A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and a fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source. The third and fourth MOS transistors may alternatively be connected to first and second input transistors and a bias transistor arranged as in a differential amplifier. At least one diode-connected transistor is included in series with at least one of the transistors which has a gate connected to an input voltage.


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