The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 1994

Filed:

Oct. 20, 1992
Applicant:
Inventor:

Frank M Wanlass, Sunnyvale, CA (US);

Assignee:

Standard Microsystems Corporation, Hauppauge, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307443 ; 307451 ; 307473 ;
Abstract

A CMOS device having many output channels at least one of which channel includes a first pair of pull-up/pull-down of transistors between a 'noisy Vcc and noisy ground', a second pair of pull-up/pull-down of transistors between a 'quiet Vcc and quiet ground', and logic to switch the transistor pairs such that initial switching of an output is powered by the noisy Vcc and ground, and maintenance of an output state is powered by the quiet Vcc and ground. Quiescent channels are decoupled from active channels and will hold their assigned output levels.


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Wanlass, Frank. (1994). Apparatus and method to prevent the disturbance of a quiescent output (U.S. Patent No. 5319260). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5319260

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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