The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 1994

Filed:

Aug. 03, 1992
Applicant:
Inventors:

Kazuhiro Sakashita, Hyogo, JP;

Shuichi Kato, Hyogo, JP;

Isao Takimoto, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257203 ; 257786 ; 257676 ; 257773 ; 437180 ; 437209 ;
Abstract

A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.


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