Multi-port memory device having precharged bit lines

Abstract

A multi-port memory device has a memory cell array including one or more memory blocks each of which has a plurality of memory cells arranged in rows and columns, and a plurality of dummy cells, with one dummy cell being provided for each row of memory cells in each of the memory blocks so that the dummy cells are connected with associated ones of the word lines extending in the row direction. The dummy cells are further connected with dummy cell bit lines extending in the column direction. Sense amplifiers are connected to receive outputs of those memory cells in the memory cell array which are selected in a memory cell selection operation and outputs of those dummy cells among the plurality of dummy cells which are selected in the memory cell selection operation for amplifying differences between the selected memory cell outputs and the selected dummy cell outputs. Precharging and shielding arrangements are also provided for improved operation.