The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 1994

Filed:

Mar. 10, 1992
Applicant:
Inventor:

Kiyofumi Ochii, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365149 ; 365201 ; 3072961 ; 3072963 ;
Abstract

A semiconductor memory device which comprises memory cells arranged in rows and columns on a semiconductor substrate, each having one transistor and one capacitor, word lines each connected to memory cells in the same row, bit lines each connected to memory cells in the same column, a plate voltage generating circuit for generating a capacitor plate voltage at the time of normal operation, a negative pulse generating circuit responsive to a control signal supplied thereto at the time of voltage stress testing, for generating a pulse voltage of negative polarity, switch circuits for supplying the pulse voltage of negative polarity output from the negative pulse generating circuit, to the plate electrodes of the capacitors of all memory cells simultaneously, in place of the output of the plate voltage generating circuit, and a switch control circuit responsive to a control signal supplied thereto during voltage stress testing, for controlling the switch circuits.


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