The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 1994
Filed:
Oct. 16, 1992
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A level converting circuit has a function of converting an input signal of a first logic level into an output signal of a second logic level. The level converting circuit includes a first transistor responsive to an input signal IN for charging an output node to the ground potential, a second transistor responsive to the input signal IN for lowering the potential of the output node to the negative potential VEE, a third transistor responsive to the potential of the output node for controlling operations of the second transistor, and fourth and fifth transistors responsive to a delay signal with delay to an output of the level converting circuit for controlling the amount of current flowing through the output node. An inverted, amplified signal of the output node is applied to the gate of the fourth transistor, and a non-inverted, amplified signal of the output node is applied to the gate of the fifth transistor. The fourth and the fifth transistors serve to enhance the potential change of the output node by the delay signal (amplified signal). As a result, a level converting circuit carrying out a switching operation at a high speed in response to the input signal IN can be implemented.