The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 1994
Filed:
May. 29, 1991
Kiyofumi Ochii, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A MOS transistor has a floating gate, which forms a memory cell of EPROM, and a control gate. The control gate is formed of a thin film. An impurity concentration of a region corresponding to the floating gate is lower than that of the other regions. The region having low impurity concentration functions as a channel region of a thin film transistor. The floating gate functions as a gate of the thin film transistor. In the memory cell in which an electron is written in the floating gate, a threshold voltage of the thin film transistor rises, and the thin film transistor is set to be in an off state. In the memory cell in which no electron is written in the floating gate, the threshold voltage of the thin film transistor lowers, and the thin film transistor is set to be in an on state. If the voltage of said control gate rises in a reading operation, an inversion layer is formed in the only cell of the erasing state and the high voltage of the control gate is supplied to a channel region, and the MOS transistor is turned on. Due to this, the voltage, which is higher than the threshold value of the memory cell of the writing state, can be supplied to the control gate.